The miniaturization of semiconductor devices and the like is advantageous in bringing about an improvement in performance and function (higher-speed operation, lower power consumption, etc.) and a reduction in cost and thus has been accelerated more and more. The lithography technique has been supporting this miniaturization and transfer masks are a key technique along with exposure apparatuses and resist materials.
In recent years, use has been made of photomasks applied with the resolution enhancement technology (RET) such as the phase shift technique. A phase shift mask is a photomask that can improve the resolution of a transfer pattern using interference of light caused by a phase shifter.
Normally, inasmuch as the photolithography is performed by reduced projection exposure in microprocessing of a semiconductor substrate, a pattern of a transfer mask has a size about four times that of a pattern to be formed on the semiconductor substrate. However, in the photolithography according to the semiconductor design rule of DRAM half-pitch (hp) 45 nm and onward, the size of a circuit pattern on a mask is smaller than a wavelength of exposure light. Therefore, if reduced projection exposure of a circuit pattern is carried out using a transfer mask formed with a transfer pattern according to the design, the shape of the transfer pattern cannot be exactly transferred onto a resist film on a semiconductor substrate due to the influence of exposure light interference or the like.
Under these circumstances, as a mask employing the resolution enhancement technology, use is made of an OPC mask or the like applied with a technique of correcting an optical proximity effect, which degrades the transfer characteristics, by performing optical proximity effect correction (OPC) (see, e.g. JP-A-H10-69055 and corresponding U.S. Pat. No. 5,851,702). For example, it is necessary to form on the OPC mask an OPC pattern (e.g. an assist bar or a hammer head having a line width less than 100 nm) having a size half or less of that of the circuit pattern.